Cekli, Serap2024-07-122024-07-1220181582-74451844-760010.4316/AECE.2018.020032-s2.0-85047844169https://dx.doi.org/10.4316/AECE.2018.02003https://hdl.handle.net/20.500.12415/7720In this study, a simple lifting based pipeline DWT (Discrete Wavelet Transform) architecture is proposed for the operation of the CDF 5/3 (Cohen-Daubechies-Feauveau 5/3) filter. This scalable architecture is faster and capable of fulfilling the transformation utilizing the parallel processing operation units. The symmetric boundary extension method is used at the signal boundaries to obtain the best result in the case of 1D/2D. The proposed architecture utilizes the hardware resources in a quite efficient way by means of the pipeline technique. The architectural design is constituted by using RTL (Register Transfer Level) design process and coded by the Verilog HDL. The proposed architecture is tested for several 1D/2D inputs to examine its operation. The related architecture is synthesized for the FPGA board to check the results. The reverse operation is fulfilled by using the same structure only by changing the shift amounts of the shifting units. The DWT coefficients are calculated on this architecture for the 1D/2D situation. The hardware resources are used effectively by utilizing the constituted architecture in folded structure in the 2D case. Satisfying results have been obtained when the different numbers of parallel processing units are utilized.eninfo:eu-repo/semantics/openAccessdigital systemsdiscrete wavelet transformsmultiprocessing systemspipeline processingprogrammable logic arraysArticle262Q31718WOS:000434245000003Q4