FPGA implementation of vedic signed multiplier
Küçük Resim Yok
Tarih
2009
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Maltepe Üniversitesi
Erişim Hakkı
CC0 1.0 Universal
info:eu-repo/semantics/openAccess
info:eu-repo/semantics/openAccess
Özet
Vedic mathematics is the name given to the ancient Indian system of mathematics. To be precise, a unique technique of calculations based on simple rules and principles with which any mathematical problems related to arithmetic, algebra, geometry or trigonometry can be solved. The system was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). The system is based on 16 Vedic sutras or aphorisms [1], which are actually Vedic mathematical for- mulae describing natural ways of solving a whole range of mathematical problems. The Vedic mathematics approach is totally di®erent and considered very close to the way a human mind works. A large amount of work has so far been done in understanding various methodologies (sutras). The need for high speed processing has been increasing as a result of expanding signal processing and computer applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real time signal and image processing applications. One of the important arithmetic operations in such applications is to perform a large number of mathematical calculations in a very less time. Since in performing mathematical calculations especially multiplication, a computer spends a considerable amount of its processing time, an improvement in the speed of a math coprocessor for performing multiplication will increase the overall speed of the computer. There are several multiplier algorithms that can be implemented such as: Array, Booth, Carry save, modifled Booth algorithms and Wallace tree. The most signifl cant aspect of the multiplier architecture of ancient Indian Vedic mathematics is that it is based on vertical and crosswise structure of ancient Indian Vedic mathematics as in [1] and [7]. In this paper a signed binary multiplication algorithm is presented based on ancient Indian Vedic mathematics. The signed multiplication algorithm is realized using verilog coding, simulated with Modelsim and implemented on Xilinx Spartan2 XC2S100-PQ208 Field Programmable Gate Array (FPGA). The paper explains 8X8 multiplication of signed binary numbers, its realization and implementation, which can be extended to a NXN signed binary numbers. The system works satisfactorily under ideal condition and is tested for multiplying various combinations of signed and unsigned 8 bit binary numbers. From the synthesis report of both the proposed algorithm and the booth algorithm [8] it is observed that the maximum combinational path delay was found to be 47.706 ns which are found to be less than Modi¯ed Booth's algorithm that requires 67.961ns implemented on the same device. Not only the time required for the multiplication is less but also the hardware utilization is also found to be less by 2% which is very signi¯cant in case of VLSI design. The signed multiplier algorithm discussed in this paper can be substituted in [2] { [7] in case if it is really required to use signed and unsigned numbers.
Açıklama
Anahtar Kelimeler
Vedic mathematics, FPGA, Signed binary multiplication
Kaynak
International Conference of Mathematical Sciences
WoS Q Değeri
Scopus Q Değeri
Cilt
Sayı
Künye
Padiyar, Y., Mandi, M. V., Ramesh, S. ve Dileep, D. (2009). FPGA implementation of vedic signed multiplier. Maltepe Üniversitesi. s. 388.
