Studies on sensitivity of clock and data recovery circuits to power supply noise
Küçük Resim Yok
Tarih
2009
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Maltepe Üniversitesi
Erişim Hakkı
CC0 1.0 Universal
info:eu-repo/semantics/openAccess
info:eu-repo/semantics/openAccess
Özet
This paper deals with the study of the impact of power supply noise on the performance of CMOS Clock and Data Recovery (CDR) Circuits. The sensitivity of the various blocks of the dual loop CDR circuit to power supply noise is first studied and then it is demonstrated that insertion of suitable Low Dropout Regulators (LDO) can enhance the performance of the CDR system with respect to power supply noise. Based on extensive simulations, it was observed that while the system can tolerate only about 20 mV/10MHz noise on the power supply, incorporation of LDOs enables it to tolerate 200mV/10MHz noise without degradation in performance.
Açıklama
Anahtar Kelimeler
Kaynak
International Conference of Mathematical Sciences
WoS Q Değeri
Scopus Q Değeri
Cilt
Sayı
Künye
Mahmoud, K. I., Rajasekar, R., Devi, J. Dhurga ve Ramakrishna, P. V. (2009). Studies on sensitivity of clock and data recovery circuits to power supply noise. Maltepe Üniversitesi. s. 228.
