Studies on sensitivity of clock and data recovery circuits to power supply noise

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dc.contributor.authorMahmoud, Khalil I.
dc.contributor.authorRajasekar, R.
dc.contributor.authorDevi, J. Dhurga
dc.contributor.authorRamakrishna, P. V.
dc.date.accessioned2024-07-12T20:50:13Z
dc.date.available2024-07-12T20:50:13Z
dc.date.issued2009en_US
dc.departmentFakülteler, İnsan ve Toplum Bilimleri Fakültesi, Matematik Bölümüen_US
dc.description.abstractThis paper deals with the study of the impact of power supply noise on the performance of CMOS Clock and Data Recovery (CDR) Circuits. The sensitivity of the various blocks of the dual loop CDR circuit to power supply noise is first studied and then it is demonstrated that insertion of suitable Low Dropout Regulators (LDO) can enhance the performance of the CDR system with respect to power supply noise. Based on extensive simulations, it was observed that while the system can tolerate only about 20 mV/10MHz noise on the power supply, incorporation of LDOs enables it to tolerate 200mV/10MHz noise without degradation in performance.en_US
dc.identifier.citationMahmoud, K. I., Rajasekar, R., Devi, J. Dhurga ve Ramakrishna, P. V. (2009). Studies on sensitivity of clock and data recovery circuits to power supply noise. Maltepe Üniversitesi. s. 228.en_US
dc.identifier.endpage229en_US
dc.identifier.isbn9.78605E+12
dc.identifier.startpage228en_US
dc.identifier.urihttps://hdl.handle.net/20.500.12415/2291
dc.language.isoenen_US
dc.publisherMaltepe Üniversitesien_US
dc.relation.ispartofInternational Conference of Mathematical Sciencesen_US
dc.relation.publicationcategoryUluslararası Konferans Öğesi - Başka Kurum Yazarıen_US
dc.rightsCC0 1.0 Universal*
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.rights.urihttp://creativecommons.org/publicdomain/zero/1.0/*
dc.snmzKY07618
dc.titleStudies on sensitivity of clock and data recovery circuits to power supply noiseen_US
dc.typeConference Object
dspace.entity.typePublication

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